View KS7301B_420624.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

KS7301B
GENERAL DESCRIPTION
KS7301B is a CMOS IC designed for Digital Camcorder System. This Processor is Compatible for NTSC/PAL & Hiband/Normal Camcorder System.
DIGITAL CAMERA PROCESSOR
160-QFP-2424
FEATURES
- Luminance & Chroma Signal Procession - Built in Timing Generator - Built in Sync. Generator - Built in Memory for Detection Part (16bit* 64 word*2 page) - Built in 1H delay line (1H *2, 8 bit *910) - Built in Encoder for PAL/NTSC - Built in DIS Interface Block - Built in Super Impose function - Built in Title Mix Block - Compatible with NORMAL/Hi - Band System - Built in Micro controller Interface Block
ORDERING INFORMATION
Device KS7301B Package 160-QFP-2424 Operating Temperature -20C ~ +75C
BLOCK DIAGRAM
SDATA LD DHD DYD DISRSTN FLD LSSE
TST0
TST1
Y <7:0> C <7:0> HEODN VEODN DOS <7:0> DIS <7:0>
DM
(Detection Module)
CPM
(Color Processing Module)
MATM
(Matrix Module)
EM
(Encoding Module)
SPDAC SPDAY FSC SYNC LALT BF
M - BUS
X1 X2 X3 X4 PCK SCK H1 H2 XSG1 XSG2 ID
SSA <19:0>
TGM
(Timing Generation Module)
BIM
(BUS Interface Module)
SIM
(SuperImpose Module)
SSD <7:0> VCOL<2:0>
RESETN DCPN SAM8NECN
VBLK VDATA
SOEN SWEN SCSROMN
VVD VHD
SCSRAMN
AD<7.0> PALNTN HIB DCPCSN ASTB WRN RDN WAITN
XPG SHD SHP XSUB CLP1 CLP2 CLP3 CLP4 V1 V2 V3 V4 PBLK SPO PC
KS7301B
DIGITAL CAMERA PROCESSOR
PIN CONFIGURATION
120
116
111
106
101
96
91
86
121
BF FSC SPDAY SSA<19> SSA<18> SSA<17> SSA<16> SSA<15> SSA<14> SSA<13> SSA<12> SSA<11> SSA<10> SSA<9> SSA<8> SSA<7> VSS SSA<6> SSA<5> SSA<4> SSA<3> SSA<2> SSA<1> SSA<0> SSD<7> SSD<6> SSD<5> SSD<4> SSD<3> SSD<2> VDD
VSS Y<4> Y<3> Y<2> Y<1> Y<0> SPDAC LALT SYNC
81
126
131
136
141
146
151
156
PCK ID DISRSTN
160
Y<5> Y<6> Y<7> C<0> C<1> C<2> C<3> C<4> C<5> C<6> VDDIN C<7> SDATA LD DHD DVD VSSIN VDD LSSE FLD HEODN VEODN DIS<0> DIS<1> DIS<2> DIS<3> DIS<4> DIS<5> DIS<6> DIS<7> VDDIN DOS<0> DOS<1> VSS DOS<2> DOS<3> DOS<4> DOS<5> DOS<6> DOS<7> SCK
KS7301B
SSD<1> SSD<2> SCSRAMN SCSROMN SWEN SOEN VDATA VCOL<2> VCOL<1> VCOL<0> VSSIN VBLK SAM8NECN WD VHD VSS AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0> RWN ASN DSN WAITN DCPCSN VSSIN PC VDD RESETN H18 PALNTN VSS VSS X4 X3 DCPN
80
76
71
66
61
56
51
46
41
TST0 TST1 VDDIN
XPG XSG1 XSG2 XSUB V1 V2 V3 V4 VDD VSS X1 X2
CLP1 CLP2 CLP3 CLP4 PBLK SHD VSS SHP H1
NC NC VDD NC NC NC NC NC NC SP0
11
16
21
26
31
36
40
1
6
VDD
H2
KS7301B
PIN DESCRIPTIONS
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol SCK PCK ID DISRSTN NC NC VDD NC NC NC NC NC NC SP0 CLP1 CLP2 CLP3 CLP4 PBLK SHD VSS SHP H1 H2 XPG XSG1 XSG2 XSUB V1 V2 V3 V4 VDD VSS X1 X2 TST0 TST1 VDDIN VDD I/O O O O O O O O O O O O O O O O O O O O O O I O I I I
DIGITAL CAMERA PROCESSOR
Description Secondary Pipe Line clock ( PCK/2 ) Main Pipe Line Clock CCD Line ID Signal DZE Reset Signal ( Active Low ) No connection No connection I/O Power supply No connection No connection No connection No connection No connection No connection A/D Converter Sampling Clock Clamp Pulse 1 Clamp Pulse 2 Clamp Pulse 3 Clamp Pulse 4 Video Pre - Blanking Pulse Data Sampe & Hold Pulse For CDS Ground Pre-Charge Sample & Hold Pulse For Horizontal Driving Pulse 1 For CCD Horizontal Driving Pulse 2 For CCD Pre-Charge Gate Pulse For CCD Read Out Pulse 1 For CCD Read Out Pulse 2 For CCD Discharge Pulse For CCD Vertical Driving Pulse 1 For CCD Vertical Driving Pulse 2 For CCD Vertical Driving Pulse 3 For CCD Vertical Driving Pulse 4 For CCD I/O Power Supply Ground Main X-tal Input Main X-tal Output IC Test pin IC Test Output Power Supply (INTERNAL) Power Supply For X - tal
Remark *1
CDS
*2 *3 *3
KS7301B
DIGITAL CAMERA PROCESSOR
PIN DESCRIPTIONS (Continued)
No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol DCPN X3 X4 VSS VSS PALNTN HI8 RESETN VDD PC VSSIN DCPCSN WAITN DSN(RDN) ASN(AS) RWN AD<0> AD<1> AD<2> AD<3> AD<4> AD<5> AD<6> AD<7> VSS VHD VVD SAM8NECH VBLK VSSIN VCOL<0> VCOL<1> VCOL<2> VDATA SOEN SWEN SCSROMN SCSRAMN SSD<0> SSD<1> I/O I I O I I I O I O I I I I/O I/O I/O I/O I/O I/O I/O I/O I I I O O O O O O O O O I/O I/O Description IC Test Pin 4Fsc X - tal Input For PAL (17.73447MHz) 4Fsc X - tal Output For PAL Ground X - tal Ground PAL/NTSC Mode Select ion Pin 760H/510H CCD Mode Selection Pin IC Reset Input I/O Power Supply Phase Comparator Output Of PAL PLL Ground (INTRENAL) DCP Chip Select Pin (Low Active) Wait For Micom Interface (Low Active) Remark *3
*4
*5 *6 *7 Micro controller Address / Data Bus I / O
Ground VCR Part HD Pulse (VCR PB Mode Title Mix) VCR Part VD Pulse (VCR PB Mode Title Mix) Microcontroller Type Select Pin (SAM8:High, NEC:Low) Title Blank Signal For VCR PB Mode Title Mix Ground (INTERNAL) Title Color Signal For VCR PB Mode Title Mix
Title Data Enable Signal For VCR PB Mode Title Mix ROM Enable For Superimpose ( Low Active ) RAM Enable For Superimpose ( Low Active ) ROM Chip Select For Superimpose ( Low Active ) RAM Chip Select For Superimpose ( Low Active ) Memory Interface Data I/O For Superimpose
KS7301B
DIGITAL CAMERA PROCESSOR
PIN DESCRIPTIONS (Continued)
No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol VDD SSD<2> SSD<3> SSD<4> SSD<5> SSD<6> SSD<7> SSA<0> SSA<1> SSA<2> SSA<3> SSA<4> SSA<5> SSA<6> VSS SSA<7> SSA<8> SSA<9> SSA<10> SSA<11> SSA<12> SSA<13> SSA<14> SSA<15> SSA<16> SSA<17> SSA<18> SSA<19> SPDAY FSC BF SYNC LALT SPDAC Y<0> Y<1> Y<2> Y<3> Y<4> VSS I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Description Power supply For I/O Memory Interface Data I/O For Superimpose Remark
Memory Interface Address Output For Superimpose
Ground Memory Interface Address Output For Superimpose
Memory Interface Address Output For Superimpose
D/A Converter Sampling Clock For Y Signal (PCK) Chroma Subcarrier (NTSC : 3.7595MHz, PAL : 4.4336MHz) Burst Flag Pulse Video Composite SYNC signal Line Atternate Pulse For PAL D/A Converter Sampling Clock for C Signal (4Fsc) Y Video Signal Output
Ground
KS7301B
DIGITAL CAMERA PROCESSOR
PIN DESCRIPTIONS (Continued)
No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Symbol Y<5> Y<6> Y<7> C<0> C<1> C<2> C<3> C<4> C<5> C<6> VDDIN C<7> SDATA LD DHD DVD VSSSIN VDD LSSE FLD HEODN VEODN DIS<0> DIS<1> DIS<2> DIS<3> DIS<4> DIS<5> DIS<6> DIS<7> VDDIN DOS<0> DOS<1> VSS DOS<2> DOS<3> DOS<4> DOS<5> DOS<6> DOS<7> I/O O O O O O O O O O O O O O O O O O I I I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I Y Video Signal Output Description Remark
C Video Signal Output
Power supply (INTERNAL) C Video Signal Output DZE Interface Serial Data DZE Interface Load Signal HD signal for DIS VD signal for DIS Ground (INTERNAL) Power supply For I/O Low Shutter Speed Enable Video Field Signal Chroma S1, S2 Pixel Control (Default : High) Chroma 2R-G, G-2B Line Control (Default : High) CCD Video Input Signal
Power supply (INTERNAL) DZE Video Input Signal Ground DZE Video Input Signal
KS7301B
DIGITAL CAMERA PROCESSOR
< REMARK > *1. Main Pipe Line Clock 510H: NTSC 1820/3fh, PAL 18 6/3fh 760H: NTSC 910fh, PAL 908fh *2. Main X-tal Input NTSC:28.63636MHz, PAL:28,375Mhz *3. IC Test Pin ( TST1, TST0, DCPN) ( 0,0,0 ) : TEST ( CPM ) ( 0,0,1 ) : TEST ( MATM ) ( 0,1,0 ) : TEST ( TGM ) ( 0,1,1 ) : TEST ( SIM ) ( 1,0,0 ) : TEST ( DC LOW ) ( 1,0,1 ) : TEST ( DC HIGH ) ( 1,1,0 ) : NORMAL ( 1,1,1 ) : RESERVED *4. Phase Comparator Output Of PAL PLL Include Charge Pump Part *5. SAM 8 Mode : Data Strobe Signal Input ( Low Active ) NEC Mode : Read Enable ( Low Active ) *6. Address Strobe For Micom Interface SAM 8 : Low Active, NEC : High Active *7. SAM 8 Mode : Read / Write Enable Read : High, Write : Low ) NEC Mode : Write Enable ( Low Active )
KS7301B
ABSOLUTE MAXIMUMTINGS
Characteristics Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature
DIGITAL CAMERA PROCESSOR
(Ta=25C) Symbol VDD VIN VOUT PD T OPR T STG Value -0.5~6.5 -0.5~VDD+0.5 -0.5~VDD+0.5 1 -20~+75 -65~+150 Unit V V V W C C
ELECTRICAL CHARACTERISTICS
(VCC=5V, Ta = 25C, unless otherwise specified ) Characteristics Supply Voltage Input Leakage Current Output Leakage Current Operating Current High-Level Input Voltage Low-Level Input Voltage Output High Voltage 1 Output Low Voltage 1 *Output High Voltage 2 *Output Low Voltage 2 **Output High Voltage 3 **Output Low Voltage 3 *: XPG, SHP, SHD Pulse ** :H1, H2 Pulse Symbol VDD IU ILO ICC VIH VIL VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 Test Condition VDD=5V IOH=-2mA IOL=4mA IOH=-4mA IOL=8mA IOH=-8mA IOL=8mA Min 4.5 0.8VDD 0 VDD-0.5 VDD-0.5 VDD-0.5 Typ 5.0 140 Max 5.5 1 1 180 VDD 0.2VDD 0.45 0.45 0.45 Unit V uA uA mA V V V V V V V V Remark
*1 *1 *2 *2 *3 *3
*1 : IO=2mA *2 : IO=4mA *3 : IO=8mA
KS7301B
DIGITAL CAMERA PROCESSOR
Micro controller Interface : for SAVB ( PIN68A HIGH )
Characteristics Address setup time Address hold time ASTB pulse width ASTB, WAITN distance DSN delay from Data WRN width Data hold time Data delay from DSN Data, WAITN distance ASN, DSN distance Symbol Tast Taht Tasw Tawd Tdsdy Twrw Tdh Trdrv Tdwd Tadd Min 15 35 35 35 400 0 35 Typ Max 35 270 140 Unit nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec Remark Write Read Read
Micro controller Interface : for SAM8 (PIN68 HIGH)
DCPCSN
Tast
A D < 7 :0> ASN(AS)
ADDR
Tasw Taht Tdsdv Tawd
DATA
Tdh
DSN(RDN) RWN (WRN) W AITN
Twrw
< W R IT E M O D E >
DCPCSN
Tast
A D < 7 :0>
ADDR
Tasw Taht Tadd Trddv
DATA
Tdh
ASN(AS) DSN(RDN) R W N (WRN) W AITN
Tawd
Tdwd
< READ MODE >
KS7301B
DIGITAL CAMERA PROCESSOR
Micro controller Interface : for SAVB (PIN68 LOW)
Characteristics Address setup time Address hold time ASTB pulse width ASTB, WAITN distance Data delay from DSN WRN width Data hold time Data delay from RDN Data, WAITN distance ASN, DSN distance Symbol Tast Taht Tasw Tawd Tdsdy Twrw Tdh Trdrv Tdwd Tadd Min 15 35 35 35 400 0 35 Typ Max 35 100 270 140 Unit nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec Remark Write Read Read
Micro controller Interface : for NEC (PIN68 LOW)
DCPCSN
Tast
AD <7:0>
ADDR
Tasw Taht Tdsdv
DATA
Tdh
ASTB (AS)
Tawd Twrw
W R N (RWN) RDN (DSN) WAITN < WRITE MODE > DCPCSN
Tast
AD <7:0>
ADDR
Tasw Taht Trddv
DATA
Tdh
ASTB (AS)
Tawd
Tdwd
RDN (DSN) W R N (RWN) WAITN
< READ MODE >
KS7301B
DIGITAL CAMERA PROCESSOR
Vertical Timing for SYNC signal
(1) NTSC
FIELD VHD 9H VVD STNC
FIELD
VBLK
20H
BF FLD
FIELD VHD 9H VVD STNC 20H VBLK BF FLD
FIELD
KS7301B
DIGITAL CAMERA PROCESSOR
(2) PAL
VHD
FIELD ,
FIELD , V
7.5H VVD STNC 25H
VBLK
BF(3-4) BF(1-2)
FLD
VHD
FIELD , V
FIELD ,
7.5H VVD STNC 25H VBLK BF(34-1) BF(2-3) FLD
KS7301B
ID
DIGITAL CAMERA PROCESSOR
NTSC/NORMAL VHD FLD VVD ID
NTSC/HI8 VHD FLD VVD ID
PAL/NORMAL VHD FLD VVD ID
PAL/HI8 VHD FLD VVD ID
KS7301B
SHP, SHD, H1, H2
DIGITAL CAMERA PROCESSOR
NTSC/NORMAL OSC1 PCLK1 H1 H2 XPG SHP SHD
NTSC / HI8 OSC1 PCLK1 H1 H2 XPG SHP SHD
KS7301B
DIGITAL CAMERA PROCESSOR
XSUB (1 / 10000 sec Low Shutter Speed Mode )
NTSC 1/60 VVD VH D XSG1 XSUB
PAL
SPO
NORMAL H1 SHP SHD SP0
HI8 H1 SHP SHD SP0
~ ~
KS7301B
Horizontal Timing of V1 - V4, XSG1,XSG2
DIGITAL CAMERA PROCESSOR
ODD HD V1 V2 V3 V4
EVEN V1 V2
T1
T2
V3 V4 XSG1 XSG2 T5 unit : T6
T3
T4
Normal T1 T2 T3 T4 T5 T6 1.1 2 39.5 2.5 43.5 2.5
HI18 1.6 2.5 42.2 2.5 47.2 2.5
KS7301B
Horizontal Timing For CCD(NTSC/NORMAL)
HD
CBLK
H1
5 1 5 10 15 10 1 15 10 15 20 25 20 1 5
H2
V1
V2 V3
V4
CLP1
CLP2
CLP3
CLP4
DIGITAL CAMERA PROCESSOR
XSUB
KS7301B
Horizontal Timing For CCD(PAL/NORMAL)
HD
CBLK
5
10
15
15
1 15
10
10
20
1
5
1
5
25
30
20
V1
V2 V3
V4
CLP1
CLP2
CLP3
CLP4
DIGITAL CAMERA PROCESSOR
XSUB
KS7301B
Horizontal Timing For CCD(NTSC/HI8)
HD
CBLK
10
15
10
15
10
1 20
1 5 20 40
1
5
5
25
30
35
15
20
V1
V2 V3
V4
CLP1
CLP2
CLP3
CLP4
DIGITAL CAMERA PROCESSOR
XSUB
KS7301B
Horizontal Timing For CCD(PAL/HI8)
HD
CBLK
10
15
10
15
10
1 20
1 20 30 5 40
1
5
5
25
35
15
20
V1
V2 V3
V4
CLP1
CLP2
CLP3
CLP4
DIGITAL CAMERA PROCESSOR
XSUB
KS7301B
Vertical Timing For CCD(NTSC/NORMAL)
FLD VD
CBLK
HD
XSG1
XSG2
V1
V2
V3
V4
CCD
246 135
492
246 135
492 491
246 135
2468 1357
OUT
491
CLP1
CLP2
DIGITAL CAMERA PROCESSOR
CLP3,4
KS7301B
Vertical Timing For CCD(PAL/NORMAL)
FLD VD
CBLK
HD
XSG1
XSG2
V1
V2
V3
V4
CCD
246 135
582
246 1 35
582 581
246 135
2468 1357
OUT
581
CLP1
CLP2
DIGITAL CAMERA PROCESSOR
CLP3,4
KS7301B
Vertical Timing For CCD(NTSC/HI8)
FLD VD
CBLK
HD
XSG1
XSG2
V1
V2
V3
V4
CCD
246 135
493
246 135
494 493
246 135
2468 1357
OUT
494
CLP1
CLP2
DIGITAL CAMERA PROCESSOR
CLP3,4
KS7301B
Vertical Timing For CCD(PAL/HI8)
FLD VD
CBLK
HD
XSG1
XSG2
V1
V2
V3
V4
CCD
246 135
582
246 135
582 581
246 135
2468 1357
OUT
581
CLP1
CLP2
DIGITAL CAMERA PROCESSOR
CLP3,4
KS7301B
REGISTER MAPPING
REGISTER NAME ADDRESS NO.(HEX) BITS MODE
DIGITAL CAMERA PROCESSOR
DESCRIPTION DCP Status Register
7~3 2 PN 1 HI8 0 SB High : Superimpose Busy Low : Superimpose Stanby High :Hi8 Mode Low :Normal Mode High :PAL Mode Low :NTSC Mode
BST
00
3
R
----
DADR
20
6
W
Detection RAM Address Pointing Register Just with assignment Start point, increasing the 64 step Address automatically. To read the first small picture, set the Address value to 00(HEX) (LSB 6 bit using) Detection Data Register
15 ~ 8 DMDH 7~0 DMDL
DMDL
21
8
R/W
DMDH DCMD
22 23
8 8
R/W W
Read cycle achieve which of DMDH DMDL Register in AE/AF/AWB detection Data Command Register
7 FS1
6 FS2
5 R/B
4 R/W
3 PG
2 ADC
1 DIS
0 PHC High : AF Peak-hold Data Detection Low : AF Integration Data Detection High : DIS On Low : DIS Off High : Odd Clock Delay Low : Even Clock Delay High : Page 1 Micom Read Low : Page 0 Micom Read High : Detection RAM Read Low : Detection RAM Write High : AWB R-Y Data Detection Low : AWB B-Y Data Detection High : AE Mode Low : AF2 Mode High : AWB Mode Low : AF1 Mode
KS7301B
DIGITAL CAMERA PROCESSOR
REGISTER NAME DDIS COV1 COV2 CAG CC0A CC0B CAKP CNSL
ADDRESS NO.(HEX) 27 40 41 42 43 44 45 46
BITS MODE 8 8 8 8 8 8 8 8 WR WR WR WR WR WR WR WR
DESCRIPTION DZE Mode Control Register Knee Delta Coeff. Register ( Default : Hex 00 ) Range : 0 ~ 255( FF ) Knee Coeff. Register ( Half value of Knee Point ) Range : 0 ~ 255( FF ) Aperture Gain Register Range : 0 ~ 255( FF ) Color Coeff.1 Register ( Default : 0.12 ) Range : 0 ~ 6dB( FF ) Color Coeff.2 Register ( Default : 0.2 ) Range : 0 ~ 6dB( FF ) Knee Point Value Range : 0 ~ 255( FF ) Aperture Noise Slice Level Range : 0 ~ 255( FF ) Bdge Chroma Suppress
7 6~5 Gain 4~0 Suppress Limit Level 00: X1 01: X 1/2 10: X 1/4 11: X 2
CAPS
47
7
WR
CRC0 CBC0 CGC0 CUTH CLTH;
48 49 4A 4B 4C
8 8 8 5 5
WR WR WR WR WR
Deciding the amount of Max, Suppress by fixing the suppress Limit Level Cr(=2R-G) Gain Range : 0 ~ 6 dB ( FF ) Cb(=G-2B) Gain Range : 0 ~ 6 dB ( FF ) YL Gain Range : 0 ~ 6 dB ( FF ) Superimpose RAM Mode Input Data High Threshold Range : 0 ~ 32 ( 1F ) Superimpose RAM Mode Input Data Low Threshold Range : 0 ~ 32 ( 1F )
KS7301B
DIGITAL CAMERA PROCESSOR
REGISTER NAME MRPW MGPW MBPW MRWB MBWB MDSCR MDSCR MDSCR MRHC
ADDRESS NO.(HEX) 60 61 62 63 64 65 66 67 68
BITS MODE 8 8 8 8 8 8 8 8 8 WR WR WR WR WR WR WR WR WR
DESCRIPTION Red Pre-white Balance Coeff. Range : 0 ~ 18dB ( FF ) 0dB : HEX 20 Green Pre-white Balance Coeff. Range : 0 ~ 18dB ( FF ) 0dB : HEX 20 Blue Pre-white Balance Coeff. Range : 0 ~ 18dB ( FF ) 0dB : HEX 20 Red White Balance Coeff. Range : 0 ~ 18dB ( FF ) 0dB : HEX 20 Blue White Balance Coeff. Range : 0 ~ 18dB ( FF ) 0dB : HEX 20 RGB Black Balance Coeff. (2'C Data) Range : -127(HEX 81) ~ +127 (HEX 7F )
MBHC
69
8
WR
MRYG MBYG MA1C MB1C MA2C MB2C
6A 6B 6C 6D 6E 6F
8 8 8 8 8 8
WR WR WR WR WR WR
R-Y Hue Control Value (MRHC*[B-Y]) Range : -(B-Y) ~ +(B-Y) MSB 7 : Sign bit LSB 0 ~ 6 : Absolute Value B-Y Hue Control Value (MBHC*[R-Y]) Range : -(R-Y) ~ +(R-Y) MSB 7 : Sign bit LSB 0 ~ 6 : Absolute Value R-Y Gain Range : 0~18dB (FF) 0dB : HEX 20 B-Y Gain Range : 0 ~ 18dB (FF) 0dB : HEX 20 Color difference signal Matrix Coeff Range : 0 ~ 1 dB ( FF ) Recommand Value: MA1C : 0.7 (HEX B3) MB1C : 0.3 (HEX 4d) MA2C : 0.11 (HEX 1C) MB2C : 0.89 (HEX E4)
KS7301B
DIGITAL CAMERA PROCESSOR
REGISTER NAME EHSBY
ADDRESS NO.(HEX) A0
BITS MODE 8 WR
DESCRIPTION B-Y axis direction Burst Level (2'C Data) Range : -128(HEX 80) ~ + 127 (HEX 7F) MSB 7 : Sign bit LSB 6 ~ 0 : 2'C Value R-Y axis direction Burst Level (2' Data) C Range : -128(HEX 80) ~ + 127 (HEX 7F) MSB 7 : Sign bit LSB 6 ~ 0 : 2'C Value Chroma Fade Control Value Range : 0 ~ 6dB ( FF ) 0dB : HEX 80 White Clip Level Range : 0 ~ 255 Luminance Fade Control Value Range : 0 ~ 18dB ( FF ) 0dB : HEX 80 Set-up Level Range : 0 ~ 255 ( FF ) Blanking Level Range : 0 ~ 255 ( FF ) Command Register
EHSRY
A1
8
WR
ECFAD EWCLP EYFAD ESET EBLK ECMD1
7 EN
A2 A3 A4 A5 A6 A7
6 DVR 5 DAC
8 8 8 8 8 8
4 DAY
WR WR WR WR WR W
3 AR1
2 AR0
1 PS
0 NP 1: 0: 1: 0: 00 01 10 11 1 0 1 0 1 0 1 0 : : : : : : : : Negative Effect Normal Operation Output Pin Disable Normal Operation : Normal Operation : step16 Art Freeze : step 8 Art Freeze : step 4 Art Freeze Y D/A Clock Inverting Normal Operation Digital VCR Interface Mode Normal Operation Digital VCR Interface Mode Normal Operation Y/C Output Enable Y/C Output Disable
ECMD2
A8
5
W
Delay Adjust
7~5 ---
4, 3 Title Y/C delay daj. Range : 0~3 PCK
2~0 Y/C delay adj. Range : 0~3 PCLK
KS7301B
DIGITAL CAMERA PROCESSOR
REGISTER NAME TCMD1
7 -
ADDRESS NO.(HEX) 10
6 TSE 5 SS1
BITS MODE 7
4 SS0 3 HS3
DESCRIPTION Shutter Speed Control
2 1 HS1 0 HS0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1111 1100 1101 1110 1111 : : : : : : : : : : : : : : : : 1/60 sec (PAL 1/50 sec) 1/85 sec 1/125 sec 1/185 sec 1/250 sec 1/375 sec 1/500 sec 1/750 sec 1/1000 sec 1/1500 sec 1/2000 sec 1/2500 sec 1/4000 sec 1/6000 sec 1/10000 sec Flicker Mode
W
HS2
00 : 1/30 sec 01 : 1/15 sec 10: 1/8 sec 11 : 1/4 sec 0 : Normal 1 : Low Shutter Speed enable
ECMD2
7 6 -
11
5 4 -
1
3 -
W
2 -
Flickerless Control
1 0 FLM High : NTSC 1/120 sec, PAL 1/100 sec Low : Flickerless Mode Off
KS7301B
DIGITAL CAMERA PROCESSOR
REGISTER NAME SCMD
ADDRESS NO.(HEX) 80
BITS MODE 8 W
DESCRIPTION Superimpose Command Register
REMARK
Superimpose Instruction Set Format
7 FIL
6 OUT
5 CT1
4 CT0
3
2
1
0
Sub Instruction Code
1) TYPE 0 ( CT1=0, CT2=0) : Environmental Instruction
7 6 5 0 4 0 3 2 C2 1 C1 0 C0 000 : - - 001 : NML 010 : STOP 011 : TOG 100 : MEDi 101 : ROM 110 : SWAP 111 : - - -
* NML Conditions : -. ROM : 0 -. TOG : 0 -. MEDi : 0 -. SWAP : 0 -. PB : 0 -. TST : 0 -. DMA : 0 -. WRN : 0
2) TYPE 1 (CT1=0, CT0=0) : Configure Environment 1 (R/W, SCOLL)
7 -
6 -
5 0
4 1
3 -
2 C2
1 C1
0 C0 000 : - - - 001 : READ 010 : WRITE 011 : SCi 100 : SCo 101 : - - - 110 : - - - 111 : - - - -
Occur Superimpose Busy Flag ` while sci, sco operation Mode. 1' And, impossible to excute the other superimpose intermediate in this status. (About for 4 seconds)
KS7301B
REGISTER NAME ADDRESS NO.(HEX)
DIGITAL CAMERA PROCESSOR
BITS MODE
DESCRIPTION
REMARK
3) TYPE2 ( CT1 = 1, CT2 = 0 ) : Environmental Instruction
7
6
5 1
4 0
3 F3
2 F2
1 F1
0 F0
FIL OUT
0 : Normal Wiper 1 : Inverse Wiper 0 : Normal 1 : FILL Mode
0000 : - - 0001 :F1 0010 :F2 0011 :F3 0100 :F4 0101 :F5 0110 : F6 0111 :F7 1000 :F8 1001 :F9 1010 :F10 1011 :- - 1100 :- - 1101 :- - 1110 :- - 1111 :- - -
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
* Occur Superimpose Busy Flag ` while wiper operation Mode. And impossible to excute the 1' other superimpose intermediate in this status (About for 4 seconds) 4) TYPE 3 ( CT1 = 1, CT0 = 1 ) : Configure Environment 3
7 6 5 1 4 1 3 2 C2 1 C1 0 C0 000 : - - 001 : PB 010 : TST1 011 : DMA 100 : WRN 101 : - - 110 : - - 111 : - - -
KS7301B
REGISTER NAME SCOL ADDRESS NO.(HEX) 81 BITS MODE 7 R/W
DIGITAL CAMERA PROCESSOR
DESCRIPTION Super impose Color Status Register REMARK
7 C02
6 C01
5 C00
4 -
3 ROM
2 SWP
1 TOG
0 FIL 0 1 0 1 : : : : Medi off Medi on Toggle off Toggle on
0 : Swap off 1 : Swap on 0 : RAM Mode 1 : ROM Mode 000 001 010 011 100 101 110 111 : : : : : : : : Blank Blue Red Magenta Green Cyan Yellow White
* MSB [7 ~ 5] Color
status bit is READ/WRITE, all other bits are READ only
SDAT SPG
82 83
8 3
R/W WR
Data Register (Buffer of using at DMA test mode) Setting RAM mode stage
7 PG1 0 0 1 1
6 PG2 0 1 0 1
5 Normal Page 0 Page 1 Page 2 Page 3
4 Hi8
3 -
2 PG1
1 PG0
0 SWP
Page 0 Page 1 -
KS7301B
REGISTER NAME SADR00 SADR01 SADR02 SADR10 SADR11 SADR12 SADR20 SADR21 SADR22 SADR30 SADR31 SADR32 SADR40 SADR41 SADR42 ADDRESS NO.(HEX) 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92
DIGITAL CAMERA PROCESSOR
BITS MODE 8 8 4 8 8 4 8 8 4 8 8 4 8 8 4 WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR
DESCRIPTION ROM image 0 address register (20Bit)
REMARK
ROM image 1 address register (20Bit)
ROM image 2 address register (20Bit)
ROM image 3 address register (20Bit)
ROM image 4 address register (20Bit)
23 ~ 16 * SADR02
15 ~ 8 SADR01
4~0 SADR00
* SADR02 uses only LSB 4Bit. STH STV SSYN 93 94 95 8 8 8 WR WR WR Horizontal counter test register (Used in test) Vertical counter test register (Used in test) Title horizontal position adjusting value (After reset, 1 is set SVRT 96 8 WR and 0 is not allowed.)
Title vertical position adjusting value (After reset, 1 is set and 0 is not allowed.)
KS7301B
PACKAGE DIMENSION
DIGITAL CAMERA PROCESSOR
Unit : mm

▲Up To Search▲

Price & Availability of KS7301B

	To Download KS7301B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .